Hardcaml is a library for designing and simulating Register Transfer Level RTL hardware designs Hardcaml designs can be converted to Verilog or VHDL for use with vendor synthesis and place and route tools

Comb S Bits and Signal The module type defines the combinational logic primitives i e logical operations arithmetic multiplexers etc for Hardcaml It is implemented by both the and modules All operations work over vectors with a given bit width Each operation has rules about allowable argument widths and will raise an exception at run time if violated implements a shallow embedding of the API This means it is used to compute values directly implements a deep embedding This means it records the structure of a computation as a graph Signals also provide functions related to sequential logic registers memories and state machines In summary s are used to construct hardware designs s can be used to model combinational hardware circuits conveniently As we shall see s are also used for input and output ports of hardware simulations Circuit A circuit takes the output signals of a Hardcaml design and performs various sanity checks to ensure that it can be converted to hardware In particular we must provide input and output port names for our designs Hardware generation with Rtl A circuit can be converted to RTL with Verilog or VHDL Simulation with Cyclesim Circuits can be simulated with the module Interfaces with ppx_hardcaml An interface is a grouping of signals with associated names and bit widths A large set of functions are generated which make working with interfaces useful for constructing module ports or interacting with a hardware design in simulation The term interface is unfortunately a bit overloaded and commonly used to described mli files in OCaml a concept in Object Oriented programming and a type representing a group of signals in SystemVerilog Hardcamls use of interface is most similar to that of SystemVerilog Waveforms image will output waveforms of a simulation run as ASCII text This allows us to integrate them with standard software development style testing workflows In addition an interactive viewer application is provided for detailed analysis Comb S Bits Signal Bits Comb S # open Hardcaml Bits # let adder a b a b val adder t > t > t <fun> # adder of_string 01 of_string 10 t 11 Signal # open Hardcaml Signal # open Hardcaml Signal Unoptimized # let adder a b a b val adder Type t > Type t > Type t <fun> # adder of_string 01 of_string 10 Type t add width 2 arguments 0b01 0b10 Signal t Bits t Bits t # let c output c adder input a 8 input b 8 val c Type t wire names c width 8 data_in add # let circuit Hardcaml Circuit create_exn name my_adder c val circuit Hardcaml Circuit t <abstr> # Hardcaml Rtl print Verilog circuit module my_adder b a c input 7 0 b input 7 0 a output 7 0 c wire 7 0 _4 assign _4 a b assign c _4 endmodule unit Cyclesim let sim Hardcaml Cyclesim create circuit let a Hardcaml Cyclesim in_port sim a let b Hardcaml Cyclesim in_port sim b let c Hardcaml Cyclesim out_port sim c a Hardcaml Bits of_unsigned_int width 8 10 b Hardcaml Bits of_unsigned_int width 8 20 Hardcaml Cyclesim cycle sim # Stdio printf c %i n Hardcaml Bits to_unsigned_int c c 30 unit # type a t a a @bits 8 b a @bits 7 @@deriving hardcaml Hardcaml_waveterm

Designing hardware in Hardcaml is only part of the complete process of getting a fully working design Let s consider the typical workflow for creating a simple Xilinx FPGA design Design and simulate the circuit with Hardcaml Output a Verilog or VHDL file using Hardcaml s RTL generation functions Create a project in Vivado the Xilinx FPGA synthesis place and route tool Add board level constraints pins timing etc Synthesize place and route the design in Vivado Run static timing analysis If this fails you must correct the Hardcaml design or adjust constraints Generate a bitstream to program the FPGA For steps 1 and 2 we often use a project structure with a and directory a library containing the hardware design a test library with testbenches expect tests etc an application to generate RTL code for the Vivado toolchain bin src test src test bin