Parity

This module calculates odd parity for a 4 bit input Given a 4 bit input it outputs if it contains an odd number of s and otherwise Implemented by XORing all the bits together Verilog VHDL Hardcaml Direct translation of Verilog Direct translation of Vhdl Idiomatic Hardcaml When performing reductions in Hardcaml we will often use the tree function This rearranges the computation from into d 1 1 0 module parity input 3 0 d output q assign q ^d endmodule library ieee use ieee std_logic_1164 all use ieee numeric_std all entity parity is port d in std_logic_vector 3 downto 0 q out std_logic end entity architecture rtl of parity is begin process d is variable parity std_logic begin parity 0 for i in d range loop parity parity xor d i end loop q < parity end process end architecture let parity_1 d reduce bits_lsb d f ^ let parity_2 d let parity ref gnd in for i 0 to width d 1 do parity parity ^ d i done parity let parity_3 d tree arity 2 bits_lsb d f reduce f ^ a ^ b ^ c ^ d a ^ b ^ c ^ d